1. Field of the Invention
The present invention relates to a voltage-controlled oscillation circuit for producing an output having a frequency proportional to the value of the input voltage and a PLL (Phase Locked Loop) circuit using this oscillation circuit, and, more particularly, an improvement of an oscillation circuit capable of producing an output in a sufficient frequency range even on a low supply voltage.
2. Description of the Related Art
PLL circuits are widely used in, for example, digital display devices, radio devices and the like, as circuits to produce an output synchronous with a received signal. This PLL circuit generally has a voltage-controlled oscillation circuit, which compares the phase of an input signal with the phase of a comparison signal that is acquired by frequency-dividing an output signal by N, and produces a voltage proportional to a voltage value corresponding to the difference between those phases.
FIG. 11 is a circuit diagram exemplifying a conventional voltage-controlled oscillation circuit. This oscillation circuit comprises a voltage-current converter 1, a charge/discharge capacitor C1, comparators comp1 and comp2 and a latch circuit 16. The voltage-current converter 1 produces currents I1 and I2 proportional to the voltage value of an input voltage Vin and alters the direction of the current output according to the output of the latch circuit 16. The comparators comp1 and comp2 respectively use a lower reference voltage VRL and a higher reference voltage VRH for comparison. The voltage-current converter 1 includes a differential amplifier 15, current sources P1, P2 and P3, each comprised of a P channel transistor, which respectively produce currents i10, i11 and Il proportional to the voltage value of the input Vin, N channel transistors Q1 and Q2, which constitute a current mirror circuit, and switches SW1 and SW2.
FIG. 12 is a waveform diagram for explaining the operation of the voltage-controlled oscillation circuit. When an output Vout is at an H level, for example, the switch SW1 is closed and the switch SW2 is opened, causing the current I1 to flow toward the capacitor C1 from the current source P3. Consequently, the potential at a node A rises toward the reference voltage VRH. When the potential at the node A reaches the reference voltage VRH, the output of the comparator comp2 changes its level to an L level from an H level, causing the level of the output Vout to be changed to an L level from the H level via the latch circuit 16. As a result, the switch SW1 is open and the switch SW2 is closed, causing the current I2 to flow from the capacitor C1 to the current source I2. When the potential at node A reaches to the reference voltage VRL, the output of the comparator comp1 changes to an L level from an H level, causing the level of the output Vout to be changed to an L level from the H level via the latch circuit 16. As a result, the switch SW2 is opened and the switch SW1 is closed. The operation then returns to the initial operation.
As apparent from the above, the potential at the node A oscillates between the reference voltages VRH and VRL in accordance with the charging and discharging of the capacitor C1. This provides a clock pulse having H and L levels as the output Vout. The frequency of the output Vout then is determined by the charging and discharging speeds of the capacitor C1, which are proportional to the current values I1 and I2 proportional to the input voltage Vin. Thus, the output Vout has a frequency according to the value of the input voltage Vin.
Because of the recent tendency of the supply voltage becoming lower and lower, however, the voltage-controlled oscillation circuit shown in FIG. 11 suffers a narrower output frequency range. As the supply voltage becomes lower, particularly, the low frequency range tends to be lost.
The two comparators comp1 and comp2 receive the high reference voltage VRH and low reference voltage VRL respectively as their one input signals and receive the voltage at the node A as the other input signals. The comparator comp1 performs comparison on a voltage near the low reference voltage VRL, and the comparator comp2 performs comparison on a voltage near the high reference voltage VRH. From the viewpoint of the circuit characteristics of comparators, therefore, it is necessary to set the reference voltages VRH and VRL within the input range that guarantees the linear operation of comparators.
As the supply voltage decreases, the input range of comparators is inclined to become narrower. If the reference voltages VRH and VRL are designed to lie within that narrow input range, therefore, their voltage difference .DELTA.V (=VRH-VRL) becomes smaller. This means that the pulse width of the output Vout shown in FIG. 12 is reduced, and the output frequency range shifts toward the higher level, thus losing the low frequency band.
If the reference voltages VRH and VRL are set to the upper and lower limits of the input range that can ensure the linear operation of comparators, the operation of comparators becomes slower. This slows the response speed of the voltage-controlled oscillation circuit, shifting the oscillation frequency.
This problem may be overcome by increasing the capacitance of the capacitor C1. This solution however increases the area of the capacitor formed in the integrated circuit, and thus stands in the way of improving the integration. Alternatively, the currents I1 and I2 may be designed to be smaller, which however is not so preferable because the current values that are proportional to the input voltage Vin should be set as large as possible in order to increase the operational range of the voltage-controlled oscillation circuit.